Uart With Fifo For Serial Communication

Abstract

Universal Asynchronous Receiver Transmitter (UART) Has Continued To Be Among The Basic Serial Communication Protocols Within The Embedded Systems And Digital Design. Although Used Extensively, Traditional UART Designs Have The Disadvantage Of Losing Data In A High-continuous Rate Transmission Of Both Communicating Devices Because Of Rate Inconsistencies. The Current Paper Is Introducing A Very Solid UART Architecture With Built-in First-In First-Out (FIFO) Buffering Feature That Has Been Designed And Tested With Verilog HDL Using Standard VLSI Front-end Design. The Suggested Design Uses A Parameterizable FIFO Buffer Between Transmitter And Receiver Modules To Effectively Remove The State Of Data Overrun And Underrun And A Smooth Asynchronous Behavior Between Modules Operating At Various Clock Rates. It Consists Of The Entire System, Which Consists Of Baud Rate Generation, Serial-to-parallel Conversion System, And All-performing Frame-handling With Programmable Data-length, Parity Setting And Stop Bits. Effective Frame Generation, Data Integrity And FIFO Management Are Confirmed Through RTL Simulation Outcome With ModelSim With Several Test Conditions. The Modular Architecture Makes It Simple To Fit Into System-on-Chip Design And FPGA Implementation, And Therefore Has Been Found To Be Reliable In Communicating Even In Variably-speed Data Scenarios. Results Of Synthesis-based Optimization Have Shown The Optimal Utilization Of Areas And Timing Closure Requirements In The Face Of Conventional Constraints. In This Work, There Is An Addition Of A Reusable Intellectual Property Core That Is Applicable In Embedded Communication Systems That Need High Throughput And Low Latency Attributes.

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