Sram Size And Power Dissipation Reduction By Using 4 Storage Cells & 1 Access Transistor

Supriya Raj; Vishal Shrivastava

Volume 5, Issue 10 (October 2019)

Sram Size And Power Dissipation Reduction By Using 4 Storage Cells & 1 Access Transistor

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Volume 12 Issue 07

July 2026

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Author(s)

Supriya Raj Vishal Shrivastava

Abstract

This Paper Gives The Concept Of Using 5 Transistors SRAM So That It Can Be Utilized In The Place Of 6 Transistors SRAM. By Using DSCH2 And Microwind 2.6K I Have Design Layout Of 5T SRAM In 2.5µm And 1.5µm Technology And Perform Read And Write Operation. B

Keywords

DSCH2 Microwind SRAM DRC.

Paper ID

IJSARTV5I1033309

Publication Date

October 3, 2019

Research Area

Computer Science

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Sram Size And Power Dissipation Reduction By Using 4 Storage Cells & 1 Access Transistor

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