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Volume 12 Issue 07
July 2026
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Author(s)
E.Sudhakar B.Santhosh Kumar Sahebgoud Karaddi
Abstract
Reducing Power Consumption Is A Crucial Task For Any Circuits. Increased Demand For Portable Devices With Reduced Power Dissipation Has Put Necessary Traction To Design Low Power Circuits. Both Explicit And Implicit Pulse Triggered Flip Flops Are Designed
Keywords
Conditional Discharge Flip Flop (CDFF); Conditional Data Mapping Flip Flop (CDMFF); Clocked Pair Shared Flip Flop (CPSFF); MTCMOS; SVL
Paper ID
IJSARTV4I724345
Publication Date
July 6, 2018
Research Area
VLSI System Design