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Volume 12 Issue 07
July 2026
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Author(s)
Ms. Chaitali L Landge Prof.D.B.Pawar
Abstract
In This Work Efforts Are Made To Improve The Performance Of Full Adder With Re-spect To Power-delay Product, Power Dissipation And Time Delays Using 90nm CMOS Technology. Currently There Are Two Techniques Used Namely Alternative Internal Logic Struct
Keywords
PDP
CMOS
Paper ID
IJSARTV2I128122
Publication Date
December 14, 2016
Research Area
ELECTRONICS AND TELECOMMUNICATION ENGINEERING