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Volume 4, Issue 5 (May 2018)

Implementation Of Two Phase Clocked Adiabatic Static Cmos Logic Full Adder Design For Efficient Power Dissipation

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Volume 12 Issue 07

July 2026

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Author(s)

Dr.C.Venkatesh A.Mohanapriya

Abstract

An Efficient Power Dissipation With Adiabatic Logic Using 2 Phase Adiabatic Static CMOS Logic (2PASCL) Has Been Presented. In This Research Work Adiabatic Logic Is Mainly Used To Minimize The Energy Loss During The Operation Of The Circuit. The Adiabatic


Keywords

Adiabatic Logic Energy Recovery Full Adder Power Dissipation 2PASCL

Paper ID

IJSARTV4I523741

Publication Date

May 29, 2018

Research Area

Electronics And Communication Engineering

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