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Volume 12 Issue 07
July 2026
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Author(s)
Yudhishtir U. Bhangale Prof. Neetesh Raghuwanshi Prof. Jayant P. Bhoge
Abstract
As The Feature Size Is Continuously Decreasing And Integration Density Is Increasing, Interconnections Have Become A Dominating Factor In Determining The Overall Quality Of A Chip. Due To The Limited Scalability Of System Bus, It Cannot Meet The Requireme
Keywords
Network-on-chip
XY Routing Algorithm
Field Programmable Gate Array(FPGA)
VHDL
System-on-chip (SoC)
Latency.
Paper ID
IJSARTV3I1117939
Publication Date
November 15, 2017
Research Area
Electronics & Communication Engineering