Implementation Of Low Power Nand-based Arithmetic Circuits Using Cmos Technology With Sapon Technique

Abstract

In The Ultra Large Scale Integration (ULSI) Field, With Widespread Growing Demand For Portable And Battery-operated Electronic Devices, Power Consumption Has Become A Major Concern. Common Arithmetic Circuits Are Adders And Subtractors Which Are Important Components Of Digital Systems And Form A Significant Part Of The Total Power Dissipation Of The Circuit. Traditional CMOS Realization Of These Circuits Consumes Excessively Large Number Of Transistors, Leading To High Power Consumption, Long Propagation Delay And Silicon Silicon Area. To Solve These Problems, In This Paper, Low-power NAND-based Arithmetic Circuits Have Been Developed By 45nm CMOS Technology And Combined With The Idea Of SAPON (Self-Adaptive Power Optimization Network). To Reduce The Complexity Of The Hardware, Half Adder, Full Adder And Full Subtractor Circuits Are Achieved By Using NAND-gate-based Architectures As A Universal Logic Gate. The Technique Called 'SAPON' (sequential Active Only Power Optimum) Is Used To Optimize Switching Activity And Thus Also The Power Consumption With Correct Logical Function. The Proposed Circuits Are Designed And Simulated In Cadence Virtuoso Tool, Keeping Technology 45nm CMOS, And Performance Analysis Is Performed Based On Three Metric Parameters Of The Circuits Namely, The Number Of MOS Transistors, Power Dissipation And Propagation Delay. Through Simulation, It Has Been Found That The Arithmetic Circuits Proposed To Use SAPON Achieves Significant Power Saving With Respect To Conventional CMOS Circuits While Maintaining The Same Delay. Hence, The Proposed Approach Will Be Suitable For Low Power VLSI Applications, Portable Electronics And The Low Power Digital System Applications.

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