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Volume 4, Issue 4 (April 2018)

Implementation Of 2-bit And 4-bit Magnitude Comparator Using Fuller Adder

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Volume 12 Issue 07

July 2026

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Author(s)

Raman Shrivastava Prof.Shweta Agrawal

Abstract

In Today’s Era, The Digital VLSI Circuit Should Have Low Power, High Speed And Small In Size, These Parameters Plays Very Important Role In VLSI Designing. In This Paper We Present A New Technique To Implement 2-bit Magnitude Comparator And 4-bit Magnitud


Keywords

Full Adder VLSI Low Power Magnitude Comparator.

Paper ID

IJSARTV4I423200

Publication Date

April 29, 2018

Research Area

EC

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