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Volume 12 Issue 07
July 2026
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Author(s)
Abenayasri.S , Kavin Sitharthan.S
Abstract
This WorkRandom Access Memory (RAM) Is A Mandatory Component Of Digital System. The RAM Design Aims To Produce Faster, Smaller And Economical System. A Work On This Topic Enable Better Understanding Of Real Time Implementation On Electronic System. This Project Focuses On Designing A Random Access Memory (RAM) Module Using VHDL And Validating Its Functionality Through Simulation With Model Sim. The Objective Is To Develop A Synchronous RAM With Specified Data And Address Widths, Implement It In VHDL, And Verify Its Operation Through A Comprehensive Test Bench.
Keywords
IOT Module
Car Accident
Arduino Microcontroller
Emergency Messages
Multi Sensor
Paper ID
IJSARTV11I4103176
Publication Date
April 17, 2025
Research Area
VHDL