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Volume 5, Issue 3 (March 2019)

Design-specific Path Delay Testing In Lookup-table-based Fpgas

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7.883
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Volume 12 Issue 07

July 2026

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Author(s)

S. Sulochana

Abstract

Due To The Increased Use Of Field Programmable Gate Arrays (FPGAs) In Production Circuits With High Reliability Requirements, The Design-specific Testing Of FPGAs Has Become An Important Topic For Research. Path Delay Testing Of FPGAs Is Especially Import


Keywords

Paper ID

IJSARTV5I329607

Publication Date

March 15, 2019

Research Area

ECE

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