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Volume 12 Issue 07
July 2026
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Author(s)
M. Sreenivasula Reddy B. Umakanth
Abstract
Adaptive Clock-Gating (ACG) And Merging Flip-Flops In Which Several FFs Are Grouped And Share A Common Clock Driver Are Two Effective Low-power Design Techniques. Combining These Techniques Into A Single Grouping Algorithm And Design Flow Enables Further
Keywords
Clock Gating (CG)
Clock Network Synthesis
Low-power Design
Pass Transistor Logic.
Paper ID
IJSARTV6I839378
Publication Date
August 28, 2020
Research Area
VLSI