Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power

V.Nirmaladevi; Mrs.Angel Prabha

Volume 4, Issue 4 (April 2018)

Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power

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Volume 12 Issue 07

July 2026

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Author(s)

V.Nirmaladevi Mrs.Angel Prabha

Abstract

Clock Signal Is Considered As An Immense Source Of Power Dissipation In Synchronous Circuits Because Of Large Frequency And Load. It Does Not Carry Any Information But Consumes High Power At The Switching Activity Which Is To Be Avoided. So, By Using Cloc

Keywords

Multibit Flipflop DDCG LACG Clock Gating

Paper ID

IJSARTV4I422982

Publication Date

April 23, 2018

Research Area

Electronics And Communication Engineering

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Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power

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Volume 12 Issue 07

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