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Volume 10, Issue 1 (January 2024)

Design Of Low-power High-gain Serializer/deserializer Using Gdi Technique

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Volume 12 Issue 07

July 2026

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Author(s)

NIRMALADEVI J V. ANNAPOORANI

Abstract

CMOS Technology Is Evolving Propose And Demonstrate A Serializer/deserializer (SerDes) Toward The Testing Of Large Scale GDI Circuits With Delay-line Clocking. A SerDes, A Pair Of A Serializer (parallel-to-serial Converter) And A Deserializer (serial-to-p


Keywords

Adiabatic Logic GDI Technique Low Power High Frequency SerDes.

Paper ID

IJSARTV10I175482

Publication Date

January 8, 2024

Research Area

Electronics And Communication Engineering

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