Design And Implementation Of Multibit Full Comparator Logic In Quantum Dot Cellular Automata

Abstract

Quantum Dot Cellular Automata (QCA) Has Emerged As A Promising Nanotechnology Alternative To Conventional CMOS Circuits Due To Its Ultra-low Power Consumption, High Device Density, And Suitability For Nanoscale Computing. Among Fundamental Digital Components, Comparators Play A Crucial Role In Arithmetic Units, Control Logic, And Decision-making Circuits. This Work Presents The Design And Implementation Of An Efficient Multibit Full Comparator Using QCA Technology. The Proposed Design Employs Optimized QCA Logic Structures To Compare Multi-bit Binary Inputs And Generate Greater-than, Equal-to, And Less-than Outputs With Reduced Cell Count And Improved Layout Regularity. The Comparator Architecture Is Constructed Using Fundamental QCA Primitives And Extended Systematically To Support Multibit Comparison. Simulation Results Validate The Correct Functionality Of The Proposed Design And Demonstrate Improvements In Terms Of Complexity And Structural Efficiency. The Proposed Multibit Full Comparator Is Suitable For High-speed And Low-power QCA-based Digital Systems.

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