Design And Analysis Of Efficient Of 32 Bit Approximate Multiplier Compressors

Abstract

Approximate Computing Has Become An Emerging Technique To Reduce Power Consumption. In Numerous Applications, Multiplication Is A Crucial Operation, Designing It For Approximation Is Effective In Optimizing System Performance. In This Paper, We Propose Low-power FPGA-based Multipliers By Employing The Novel Compressor Designs. Given That The Compressor Is The Primary Unit In The Multiplier, We Introduce Novel Exact And Approximate Compressors With Low-complexity Circuits To Parallels Accumulate The Elements. To Flexibly Configure The Proposed Compressors, A Compressor-based Once-through Structure Is Proposed To 8×8 Multipliers. Two Variants Of The Approximate Multipliers Are Provided With Different Accuracy Hardware Trade-offs. Compared With The Exact Multiplier, The Proposed Approximate Multiplier Reduces Power By 57.90%, Area By 33.80%, And Delay By 24.78%. With A Similar Accuracy Loss, The Proposed Designs Save More Hardware Resources Than Others. In Addition, The Effectiveness Of Approximate Multipliers Is Assessed In Image Sharpening.

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