Impact Factor
7.883
Call For Paper
Volume 12 Issue 07
July 2026
Download Paper Format
Copyright Form
Author(s)
K.Rajesh M.Shenbagapriya R.Hemalatha G.Neelavathi
Abstract
The Flip-flop Has Two States Which Are Shown In The Below Figure. When Q=1; And Q’=0; It Is In The Set State . When Q=0 & Q’=1, It Is In The Clear State . The Outputs Of The Flip Flop Q & Q’ Are Complements Of Each Other And Are Referred To As The Normal
Keywords
FPGA(Field Programmable Gate Array)
Paper ID
IJSARTV5I329560
Publication Date
March 12, 2019
Research Area
ECE