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Author(s)
Deepak Mittal Prof. Sunil Shukla
Abstract
This Paper Describes The Design And Implementation Of Area And Delay Efficient Vedic Multiplier Using Pipeline Technique. The Hardware Kit Utilized For Implementation Is Altera FPGA Model No. EP3C16F484C6 At 65 Nm Technology At 1.2 V. The Implementati
Keywords
FPGA
Pipeline Technique
U-T Sutra
Vedic Mathematics
Vedic Multiplier
Paper ID
IJSARTV2I42081
Publication Date
April 6, 2016
Research Area
Electronics & Communication Engineering