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Volume 3, Issue 7 (July 2017)

Aging-aware Reliable Multiplier Design With Adaptive Hold Logic

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7.883
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Volume 12 Issue 07

July 2026

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Author(s)

Pranali G. Gahukar Prof. Ashish Maske

Abstract

High Speed And Low Power Consumption Is One Of The Most Important Design Objectives In Integrated Circuits. Digital Multipliers Are Most Critical Functional Units. The Overall Performance Of This System Depends On The Throughput Of Multiplier Design. Agin


Keywords

Adaptive Hold Logic (AHL) Negative Bias Temperature Instability (NBTI) Positive Bias Temperature Instability (PBTI) Reliable Multiplier Variable Latency.

Paper ID

IJSARTV3I717153

Publication Date

July 29, 2017

Research Area

E&TC

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