A Novel Pipelined Technique For Image Encryption & Decryption Based On Aes Cryptography

Abstract

The Project Presents A Fault-efficient Advanced Encryption Standard (AES) Design For Image Cryptography, Focusing On Customizing SubBytes And MixColumns, Which Are The Most Critical Hardware Components. The Proposed AES Architecture, Implemented Using Verilog HDL And Simulated In ModelSim 6.4c, Aims To Reduce Area And Delay While Maintaining High Security. Both Application-Specific Integrated Circuit (ASIC) And Field-Programmable Gate Array (FPGA) Implementations Are Targeted, With Performance Evaluation Performed Using Xilinx Synthesis Tools.An 8-bit Datapath Is Employed, Where Two Dedicated Register Banks Store Plaintexts, Keys, And Intermediate Results. To Reduce Logic Consumption, The ShiftRows Operation Is Performed In The State Register Using An I/O Combination Of A Serial Solution. Round Modules, Including SubBytes, MixColumns, And AddRoundKey, Operate In Parallel And Repeat 10 Times During Encryption And Decryption. A Global Counter Applies The EN_SIG Signal, Which Generates Critical Control Signals Such As DATA_IN_SEL, LAST_RND_SIG, And KEY_IN_SEL To Manage Data Flow Effectively.The AES Decryption Process Mirrors The Encryption Process By Reversing The Transformations In The Round Module, Ensuring Robustness And Security. This Design Is Particularly Suitable For Lightweight, Resource-constrained IoT Devices, Addressing Growing Concerns About Data Privacy And Unauthorized Access. By Customizing The AES Datapath, The Proposed Architecture Reduces Hardware Footprint And Clock Cycles, Making It Highly Efficient For Real-time Cryptographic Applications. The Modular And Parallel Structure Of The Design Enhances Processing Speed While Maintaining The Required Security Standards.Overall, The Presented AES Accelerator Ensures A Balance Between Security, Fault Efficiency, And Performance, Making It Ideal For Secure Image Encryption In IoT And Embedded Systems.

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