Impact Factor
7.883
Call For Paper
Volume 12 Issue 07
July 2026
Author(s)
Mr. Snehal Kumbhalkar Mr. Sanjay Tembhurne
Abstract
In The Modern Era, Power Dissipation And Area Of The Circuit Under Fabrication Has Become A Major And Vital Constraint In The Electronic Industry. The Objective Of This Paper Is To Reduce The Power Dissipation In The Circuit By Using Gate Diffusion In
Keywords
Gate Diffusion Input
Full Adder
Half Adder
Paper ID
IJSARTV2I31862
Publication Date
March 15, 2016
Research Area
VLSI