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Volume 12 Issue 07
July 2026
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Author(s)
T Madhu A. Suresh Babu Vidadala Srija
Abstract
This Paper Presents A Novel Architecture Of Pulse Triggered And Edge Triggered SISO & SIPO Registers. We Are Going To Analyze Their Quantum Cost, Delay And Garbage In Terms Of Some Lemmas. We Will Explain With An Example Of Sequence Pulse Generation With
Keywords
LFSR
PSA
Encryption
Decryption
Reversible
VHDL.
Paper ID
IJSARTV6I838270
Publication Date
August 5, 2020
Research Area
ECE